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Is it possible to input only HPS_CLK1 when using MAIN_CLK, Peripheral_CLK, SDRAM_CLK, and OSC1_CLK at the same frequency in Cyclone V SoC?
SoC FPGA
clock/PLL
Category: SoCs
Tools: Quartus® II
Device: Cyclone® V
When operating at the same frequency, there is no problem with only HPS_CLK1.
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