Buffer + level shifter function can be integrated!÷2, ÷4 frequency division function by switching H/L of external pin!
Introducing Universal Clock Buffer Si5330x Series
Product Summary
The Si5330x series is a clock buffer that supports various formats with low jitter. There is a lineup of 2 to 10 channels, and the optimal model number can be selected according to the presence or absence of functions. The integrated LDO and high performance in power supply noise rejection eliminates external components and leads to a smaller footprint. A variety of output clock formats can be selected using the high/low switching by an external input pin and the level shifter function.
*For details, please refer to the model number table and data sheet described later, and use this article to select the model number of the Si5330x series.
Product features
1. Low jitter 50 fs rms (when input frequency is 625 MHz)
2. Lineup of 2~10ch
3. Supported input formats (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS)
4. Input frequency range: 1MHz~725MHz
5. Individual settings for each bank (frequency division function, format conversion, output enable, level shifter)
6. Input selection and change possible with one multiplexer for two input signals
7. Confirmation of input signal status by loss of signal (LOS)
8. 3 patterns of division function (÷1, ÷2, ÷4)
9. Operating Temperature Range TA -40~85℃
How to choose an output format
The Si5330x can select various output clock formats for each bank, as shown in the table below, by switching the High/Low/Open (Middle)* level to the external input pin (SFOUTx) and the VDDOX input power supply.
Also, if you want to reduce EMI, you can set the drive current value in 4 patterns of LVCMOS by the value of VDDO.
*Open: Pull-up and pull-down resistors are built into the SFOUTx pin, so the potential of the SFOUTx pin when open is VDD/2, that is, the middle level between High (VDD) and Low (GND). will be
Divide function
As an additional function of the Si53301/02/03/08, each bank has a divider, and 3 patterns of division ratio can be selected by an external input pin (DIVx). Specifically, as shown in the table below, it is divided by 2 when connected to pull-down, divided by 4 when connected by pull-up, and divided by 1 when not connected (Open). If you want to use the input = output clock frequency without changing the frequency, like a general clock buffer, leave the DIVx pin open.
Product details
If you want to know more specific product details, please check the data sheet below.
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