Introduction video

[movie]
Introducing Questa CDC

Document

[Material (PDF)]
let's try it! Questa CDC Tutorial
Import FPGA project for CDC analysis

<Environment construction>

Please refer to here for downloading and installing Questa CDC.

<Application for evaluation license>

If you do not have a license and would like to try out HyperLynx DRC, please contact us to request an evaluation license.

▶Inquiries (request for evaluation license), etc.

Please write "I would like an evaluation license". The person in charge will contact you.

Feature introduction

For multi-clock domain designs, simulation cannot accurately predict data transfers between different clock domains. Therefore, by analyzing the circuit structure that tends to cause problems in advance, countermeasures can be taken from the initial stage of design.

A problem in multi-clock domain designs is metastability. Metastability occurs when the timing of the transmit clock and the receive clock do not match, causing setup/hold timing violations. When metastability occurs, the received signal goes through an unstable state and then converges.

Each feature of Questa CDC is here.

CDC structural analysis

Automatically detect clocks in your design, perform CDC analysis between asynchronous data transfers, and generate reports. And it warns the CDC that the countermeasure circuit is not put in.
You can identify the RTL parts that need countermeasures and visually confirm them.

Metastability verification

Siemens EDA's patented metastability inductor (automatic metastability generator) randomly generates metastability that can occur from the circuit configuration, enabling verification close to actual machine operation. .

Assertion validation for protocol checks

This is done to check if the verification points inside the FPGA are working as intended.
ModelSim DE's built-in assertion validation uses the assertion language, while Questa CDC automatically inserts checks.

Related information

▶ How to download the Siemens EDA tool
▶ How to install Questa CDC/Formal
▶ How to license Siemens EDA tools

Seminar/Workshop

▶ [Online Seminar] How to identify asynchronous clock domains that are often overlooked -FPGA version- <free>

As the operating frequency of FPGAs increases, the number of clock domains and the number of registers increase, metastability occurs due to data transfer between asynchronous clocks (Clock Domain Crossing: CDC) in the circuit, and malfunction problems are increasing. This seminar will discuss the metastability issue and how to validate it using Questa CDC.

▶ Events and seminars related to Siemens EDA

Inquiry