What language are you using for RTL design?
SystemVerilog is a language whose number of users is rapidly increasing recently.
Therefore, for those who do not know much about SystemVerilog, I will briefly introduce the charm of SystemVerilog in two parts, the basic part and the application part.
This basic edition focuses on the benefits that can be obtained by simply introducing SystemVerilog at no cost.
In the next installment, I will introduce how to make the most of the merits of SystemVerilog, even though it costs money.
What is SystemVerilog?
SystemVerilog is a language based on Verilog-HDL, which has been used for many years, with many improvements.
It not only covers the shortcomings of Verilog-HDL, but also incorporates useful features such as VHDL, SystemC and C++ and the latest verification methods, making it an IEEE standard. The introduction of SystemVerilog not only significantly reduces RTL design and verification time, but also improves design reusability and circuit quality.
Advantages of SystemVerilog
1. Much less RTL to write!
SystemVerilog is devised to reduce the amount of description with the same amount of information as Verilog-HDL. In particular, the test bench can be reduced to a fraction of the size, so many people who used to write test benches in C++ have migrated to SystemVerilog. So how do we reduce the amount of RTL to write?
(1) Deletion of redundant descriptions
Verilog-HDL is cumbersome to declare "port name" and "type" many times. Verilog-HDL connects through the ports of "modules", so redundant port and type declarations for each "module" connected to the bus was a lot of work. SystemVerilog can omit the port name when the port name and net name are the same. Not only is the description shorter, but it is also convenient for reuse of designs because it prevents omission of corrections when port names are changed.
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module alt_tec1 (
output[31:0] d_out, |
The signal name is not required even in the always statement.
(2) Multidimensional and Enumerated Arrays
(a) Multidimensional array
Verilog-HDL only supports one-dimensional arrays, but SystemVerilog supports multi-dimensional arrays. Access to the array becomes easier and the amount of description is reduced.
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logic [3:0][1:0][7:0] mem[255 : 0 ] ; |
(b) enumerated data types
Supports enumerated data types. Enumerated data types let you name numbers, so each state machine state value has a meaningful name, and waveform groups in simulation results are labeled with states such as "Red" instead of numbers such as "01001". It is convenient because it can be displayed with the name of
Verilog-HDL is described below,
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parameter Red = 0, Green = 1, Yellow = 2; |
SystemVerilog can be defined in one line. You'll get a better idea of the design.
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typedef enum reg {Red, Green, Yellow} signal; |
(3) Object-oriented
In the software industry, C++ adopted an object-oriented approach to deal with increasingly complex programs.
And SystemVerilog also supports its major features. By using this function to perform the same processing as a function, you can efficiently create a highly reusable testbench on the testbench side.
Since the explanation is long, please ask a software engineer for details.
struct:
It combines related variables of different types and sizes into one variable. Each value in a structure can be assigned to its own memory region, but a union assigns values to a single memory region.
union:
Similar to structs, unions allocate values in a single memory area. This is useful when extracting data from a single memory area. Each value can be accessed by member name.
class:
An extension of structs that can have data and functions.
For example, if you define the formula to find the area of a circle as "circle class" and put the radius value into the "circuit class" function in your testbench, you will automatically get the "circle area value". . This "circuit class" can be used in other designs, so it will come in handy the next time you build a testbench. Of course, you don't need to verify the contents of the designed "circle class" the next time you design it. Designing with reuse in mind is important for reducing development man-hours.
2. Faster simulation speed!
SystemVerilog greatly reduces the amount of logic and testbench descriptions, so it is natural that the simulation speed will be faster, but it is also devised to speed it up.
(1) Support binary data type
Data types in Verilog-HDL are 4-valued, but SystemVerilog now supports 2-valued data types. Using binary types in the early stages of design not only reduces memory usage, but also speeds up simulation.
(2) Time unit and time precision can be specified for each module
Verilog-HDL could not specify the time unit and time precision for each module, but SystemVerilog can now specify it for each module.
Blocks that have been verified and do not require precision are loosened in time precision, and unverified blocks are simulated with increased precision to increase the overall simulation speed.
(3) Copy data array
Since Verilog-HDL can only access one array at a time, it makes heavy use of loops, as shown below.
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for (i=1; i<=256; i=i+1); |
SystemVerilog is faster because it copies the entire array at once without looping.
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Out_data = In_data; |
(4) Interface with C program
Verilog-HDL used PLI to interface with C programs, but had a problem of large overhead. SystemVerilog now supports DPI (Direct Programming Interface), which enables faster interface with C programs and faster simulation when using C programs.
3. Description errors are reduced!
(1) Compact RTL and better design visibility
1. , I explained that SystemVerilog reduces redundant descriptions, but it prevents careless mistakes when changing port names. Also, the more compact the RTL, the more predictable the design and the less mistakes you will make. In particular, it reduces mistakes when revising and reusing designs.
(2) Support new syntax
Support new syntax to reduce mistakes.
(a) The always statement as intended by the designer
When using the always statement in Verilog-HDL, if care is not taken, a circuit different from the circuit intended by the designer may be synthesized. So new always statements (always_comb/always_ff/always_latch) are now supported to generate combinatorial circuits/registers/latches as intended.
(b) Cycle-based testbench description
Verilog-HDL specifies the description of the testbench in terms of time even in synchronous design. SystemVerilog now supports a cycle-based description of "clocking", since many mistakes were made when adjusting delays.
(c) Defining Parallelism and Priority
When each condition can be processed in parallel in an if statement or case statement, use “unique”. Conversely, when each condition has a priority, use “priority” to determine whether parallel processing is possible or not as the designer intends. You can specify whether you have
(3) Relaxation of variables
In Verilog-HDL, even combinatorial circuits used“reg”, and there were many mistakes in the proper use of “reg” and “wire”, but in SystemVerilog everything can be declared with “logic”.
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4. Very easy to install!
Even if a new language has many advantages, it is difficult to implement if there are new costs, the inability to handle existing design assets and design flows, and the inability to handle other companies' tools.
In that respect, SystemVerilog also supports Verilog 2001 syntax, so you can gradually learn new syntax and migrate from Verilog-HDL to SystemVerilog without changing your existing design method.
Of course, Altera's free Quartus®II Web Edition and ModelSim®-Altera Strarter Edition have been supporting SystemVerilog as standard for several years. (*Some syntaxes are not supported.)
Next time, I'll show you how to take full advantage of SystemVerilog's features.
Appeal of SystemVerilog 2 (Utilization)