-- Testbench File for MAX(R) 10 FPGA Evaluation Kit or Intel(R) Cyclone(R) 10 LP FPGA Evaluation Kit ##

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library modelsim_lib;
use modelsim_lib.util.all;

entity testbench is
end testbench;

architecture rtl of testbench is

	constant	cycle 	: time	:= 20 ns;
	constant	half	: time	:= 10 ns;

	signal	OSC_CLK	:	std_logic;
	signal	RESET	:	std_logic;
	signal	BUTTON	:	std_logic;
	signal	LED		:	unsigned (3 downto 0);

	signal moni_pllc0 	: std_logic;
	signal moni_cnt	: unsigned (31 downto 0);
	
	component my_first_fpga 
		PORT
		(
		OSC_CLK	: in std_logic;
		RESET	: in std_logic;
		BUTTON	: in std_logic;
		LED		: out unsigned (3 downto 0)
		);
	end component;


begin

	u1 : my_first_fpga
		port map (
			OSC_CLK => OSC_CLK,
			RESET => RESET,
			BUTTON => BUTTON,
			LED => LED
			);

	CLK : process begin
		OSC_CLK <= '0';
		wait for half;
		OSC_CLK <= '1';
		wait for half;
	end process CLK;
	
	CLR : process begin
		RESET <= '1';
		wait for 35 ns;
		RESET <= '0';
		wait for cycle * 3;
		RESET <= '1';
		wait;
	end process CLR;
	
	SW : process begin
		BUTTON <= '1';
		wait for cycle * 10000000;
		BUTTON <= '0';
		wait for cycle * 5000000;
	end process SW;

	MONITOR_PLL : process begin
		init_signal_spy ("/testbench/u1/pll_inst/c0", "/testbench/moni_pllc0", 0);
		wait;
	end process MONITOR_PLL;

	MONITOR_CNT : process begin
		init_signal_spy ("/testbench/u1/simple_counter_inst/cnt", "/testbench/moni_cnt", 0);
		wait;
	end process MONITOR_CNT;
	
end rtl;