SiC Cascode JFET Approaches the Ideal Switch

Approaching an ideal practical switch is not necessarily a big leap.​ ​Combining a simple vertical trench SiC JFET with a silicon MOSFET results in a robust part with even lower normalized overall losses, easier and less critical gate drive, and higher avalanche and short circuit ratings. This device is a SiC cascode JFET,​ ​as shown in Figure 1 (right) and compared to the SiC MOSFET on the left. In the SiC cascode JFET, the channel resistance Rchannel of the SiC MOSFET is replaced by the resistance of a low-voltage Si MOSFET, resulting in much improved inversion layer electron mobility and lower losses.

Also, the SiC cascode JFET has a smaller die area in comparison, especially since it employs a package with a Si MOSFET stacked on top.

Figure 1: Comparison of architectures between SiC MOSFET (left) and SiC cascode JFET (right)

To compare the actual performance, "Figure of Merit (FoM)" This FoM combines the conduction and switching loss contributions of different applications at a given die size, which has important implications for yield and therefore cost per wafer. Figure 2 The company is comparing available 650V SiC MOSFETs with ON Semiconductor's 750V, 4th Generation SiC Cascode JFET This is a comparison of the following. RDS(ON) xA (on-resistance per unit area) is the key FoM; the lower it is, the smaller the die area for a given loss performance and the higher the yield per wafer.

Another FoM RDS(ON)xEOSS (The product of on-resistance and output switching energy characterizes the trade-off between conduction losses and switching losses, which is important in hard-switching applications._{RDS(ON)xCOSS (tr)}shows the relative efficiency performance of high frequency soft switching circuits in terms of the relationship between on-resistance and time-dependent output capacitance. Also, an important comparison is the forward voltage drop of the built-in diode.

SiC Cascode JFETIn the figure, VF is the sum of the body diode drop of the Si MOSFET and the resistance drop of the JFET in the third quadrant, which sum is on the order of 1 to 1.5 V. For SiC MOSFETs, this number can be 4 V or more, which causes significant conduction losses in the switching dead time in applications where the current is rectified by an internal diode. The on-resistance related FoM in the figure is shown at 25°C and 125°C, demonstrating the superior performance of SiC cascode JFETs in real-world environments.

Figure 2: FoM comparison of SiC cascode JFET and SiC MOSFET

3.6kW SiC Cascode JFET Totem-Pole PFC Stage Demonstrator Achieves Peak Efficiency of 99.3%

The performance of SiC cascode JFETs is perhaps best illustrated in a classic application: the totem-pole PFC stage. This circuit has long been known to be a highly efficient solution for combining AC line rectification and power factor correction, but it experiences hard switching at high power output, resulting in switching losses that are unacceptable in silicon MOSFET technology.

The solution to this problem is SiC cascode JFETs, which have shown a peak efficiency of 99.3% at 230V AC in a 3.6kW demonstrator from ON Semiconductor, helping to more easily achieve the efficiency rating of 80+ Titanium systems (Figure 3). The two 18 milliohm SiC cascode JFETs in the "fast" leg of this circuit dissipate only 8W each, while the "slow" leg uses silicon MOSFETs as synchronous AC line rectifiers. Replacing these with silicon diodes provides a lower cost solution while still achieving 99%+ efficiency. Figure 3 also shows the results of 60 milliohm SiC cascode JFETs in parallel and one 18 milliohm SiC cascode JFET per switch in the "fast" leg.

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