Basic Configuration of PCIe SW Part 4

What is PCIe SW

Peripheral Component Interconnect express (PCIe), you may have seen this name on motherboards. Do you know PCIe Switch that uses this standard?

PCIe SW was originally a standard for accessing memory from the CPU, but now it is often used for servers and storage. In addition, even within the industry, which has not shown interest in high-speed communication, attention is now focused on high-speed communication as the amount of data increases with the advent of high-precision cameras and 5G. In this article, we will explain in order while focusing on the basic functions and features of PCIe SW.

PCIe transaction layer

In Part 4, we will explain the PCIe transaction layer.

The transaction layer is located at the top of the PCIe architecture and has the role of sending and receiving TLP (Transaction Layer Packet). Transaction classification will be explained in Part 5. This section describes packets (TLP) handled by the transaction layer. A TLP consists of a TLP header, a data payload and an optional TLP digest (ECRC).

Basic structure of TLP

When exchanging information with TLP, processing corresponding to each layer is performed. The figure below shows an example of basic processing when a TLP is received by the transaction layer on the receiving side.

Processing flow when TLP is received

The transaction layer on the side that receives the TLP judges in order whether the TLP configuration is correct or incorrect, conforms to the defined TLP type, and whether it is a request, and then executes processing. When an abnormality is detected in the contents of the TLP, it is designed to notify that the TLP is discarded or contains an abnormality.

In Part 4, I briefly explained the PCIe transaction layer. In the 5th article, I will continue to explain the basic knowledge related to PCIeSW.

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