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Two things to avoid when designing boards with many power supply systems
In this article, we will introduce two things that should be avoided for those who are designing a power supply board with many power supply systems.
In order to reduce the design risk of the power supply board, is there an untouched circuit left on the board as a result of reusing the past design assets?
As a result, do you end up adding a circuit instead of changing the circuit, or do you find it complicated because you need a matching circuit?
Also, with such a board, the risk of failure increases, and when a failure does occur, it tends to be difficult to identify the location of the problem.
We hope that this article will help you reduce design man-hours and avoid problems.
Things to avoid 1. Design discretely
In a power supply board with many systems,
・Main chip power supply sequence control
・Voltage monitoring for troubleshooting
・Trim control for correcting DC/DC output fluctuations
It is necessary to implement many functions such as
Combining all of these with discrete circuits tends to result in a very complicated design.
そのため、実機試験において思ったような性能が出ず、もし回路変更が必要になった場合の工数は非常に大きくなってしまいます。
Furthermore, the use of many ICs also leads to pressure on the board area.
To prevent this situation, why not take the plunge and stop designing with discrete components?
Especially when using mainly high-end chips, the power supply circuit tends to become complicated as described above.
2. Don't Leave Fault Logs
What signal is causing the board to stop working due to a power failure? When did the anomaly occur? It is difficult to analyze defects that have occurred in the market without knowing
Even if all possibilities are eliminated at the design stage and the product is put on the market, there should be no loss in case of a power supply board that is the source of all product operations.
Especially for a power supply board with many systems, it is important to have a function that can leave a fault log as much as possible.
Failure analysis requires fault logs recorded when signs of power failure are observed
What should I do?
One way to solve the above two points is to use a PLD with dedicated functions for power supply design.
[By using PLD...]
・ Power supply sequence control, voltage monitoring, and trim control can be easily performed with one chip.
・ Fault log can be recorded in EEPROM
Lattice has a chip that can solve these problems.
First, the PacPower series provides power sequencing, voltage monitoring and trim control without a discrete design.
Internal structure of PacPower
In addition, the ASC10 series can detect abnormalities in a short time of 64us and record various monitoring signals for voltage, current, and temperature in the built-in EEPROM.
The triggering signal and the signal to be recorded can be arbitrarily selected in the design tool.
Furthermore, depending on the fault log trigger point settings, not only actual abnormalities but also signs can be captured, which can be useful for component maintenance.
Internal structure of ASC10
Also, the design method is easy, and since the chip contains a PLD, it can be designed in a programmable way.
No special knowledge is required for this programmable design method, and software is provided so that you can design on the GUI.
The tool can be installed for free from the Lattice website, so why not give it a try?
Programmable power supply board design with GUI can reduce man-hours
Document download
I have introduced two designs that should be avoided in power supply design, but I hope that you can understand that these design man-hours and the risk of defects can be resolved by introducing a PLD.
Please take a look at the following materials for more detailed information than what is described in this article, as well as specific product names and package lineups.
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