Introduction

hello! I'm Kurami.
Right now, I am studying timing analysis of Quartus® Prime in parallel with microcomputer exercises.
Timing analysis is to analyze whether the circuit operates as expected even if signal delay is considered.
My senior, Mr. Masuo, has written an article about the outline and flow of timing analysis, so please take a look!

This time, I would like to write about what I learned while studying timing constraints for clocks in timing analysis.

What are timing constraints?

The method of giving timing constraints in Quartus is described in detail in Mr. Topu's article, so I will omit it here.

The TimeQuest Timing Analyzer supports SDC.
The SDC is in command format, so you have to remember the commands and options (arguments) used for each constraint.
It's hard, isn't it?

As you can see in Topu's article, Quartus allows you to set timing constraints graphically.
For example, if you want to give a constraint of frequency 100 [MHz] to the CLK port on the design, enter as shown in Figure 1.

Since frequency and period are inversely proportional, the value to be entered in Period is 10 [ ns ].
When you click the Insert button in Figure 1 after completing the input, the SDC Editor is displayed as shown in Figure 2.

Constraints are easily given and convenient!

When I was thinking about such a thing, a word from Mr. I, a senior senior.
"Then what do you think should be done to give a constraint of 30 [ MHz ]?"

The Period item must be entered in period ( ns ), so first convert the frequency to period.
Since frequency and period are inversely proportional,
1/30 * 10^6 = 33.3333… [ns]
becomes.

It is not possible to give an exact 30 [ MHz ] constraint if it is not divisible and becomes a recurring decimal like this.
What should I do?

After some research, I found that there are two ways.

2. Enter up to 3 decimal places in the Period field

For example, if you want to give a constraint of 30 [ MHz ], if you enter "33.333" in the Period item, it will give a constraint of 30 [ MHz ].

The reason is that the value that can be set with SDC is up to the third decimal place (the minimum that can be specified is 1 ps), so if you enter up to that point, it will be recognized as 30 [MHz].

 

I've actually given constraints in two ways, so let's take a look!

Figure 3 is the SDC file used this time. Other than the constraints on the main clock, they have already been written.

First, let's take a look at how to use the dedicated commands.
Enter the command directly on the second line in Figure 3.
Since we want to give a constraint of 30 [ MHz ] this time, enter -period 30MHz .
The name can be specified arbitrarily, so this time we want to name it CLK30MHz to make it easier to understand, so enter -name CLK30MHz.
This time the target is the CLK port on the design, so type get_ports CLK . (Fig. 4)

After the input is over, do a full compile and look at the Compilation Report, you can see that the constraint of 30.0 [ MHz ] is given. (Fig.5)

Next, I would like to verify "Enter up to 3 decimal places in the Period item".
Place the cursor on the second line in Figure 3 and right click → Insert Constraint → Create Clock.
Then, enter each item as shown in Figure 6 and press the Insert button.

Then it will look like Figure 7, so save it and try full compilation.

And when you check the Compilation Report, you can see that 30 [ MHz ] constraint is given. (Fig.8)

Summary

How to deal with when the period becomes a recurring decimal number when giving timing constraints
1. Use dedicated SDC commands
2. Enter up to 3 decimal places in the Period field
I understand that it is.