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This document runs a bare-metal sample application from the QSPI flash on the Cyclone®V SoC development kit or Arria®V SoC development kit. Altera-SoCFPGA-HardwareLib-Unhosted-CV-GNU An example of standalone execution is explained.
This bare-metal sample application is a simple application that just displays a “HelloWorld!” message over UART (no need to download the hardware design (.sof file) to the FPGA).
This document describes the following:
(1) Important products in hardware development (handoff files)
② SoC FPGA boot flow
③ How to build the bare metal sample application with DS-5
・ Start DS-5
・ Import bare metal sample application
・ Build bare metal sample application
④ How to generate Preloader for QSPI flash boot
・ What is Preloader?
・ Procedure for generating Preloader for QSPI flash boot
⑤ Example of standalone execution of bare metal application from QSPI flash
・ How to write preloader and application image to QSPI flash
・ Operation check of standalone execution
Notes:
Although this document primarily targets the Cyclone®V SoC, it also applies to the Arria®V SoC as the hard processor system (HPS) portion is nearly identical.
The main development environments used in the explanations in this document are shown below.
[Table] Major environments used in this document
| item number | item | content |
| 1 | Host PC | Host PC running Microsoft® Windows® 7 or later In this document, operation has been confirmed using Windows® 7 Professional. Note: Linux can also be used with similar commands. |
| 2 | Intel® Quartus® Prime Design Software (hereafter referred to as Quartus Prime) | A tool for developing SoC FPGA hardware. This document uses the Quartus Prime development software Standard Edition v18.1. Quartus Prime Standard Editionv18.1 Notes: It is necessary to install the Device data corresponding to the SoC FPGA mounted on the target board to be used. Please refer to the following site for how to install Quartus Prime. Quartus® Prime & ModelSim® Installation Instructions |
| 3 | Intel® SoC FPGA Embedded Development Suite Standard Edition (hereafter SoC EDS) | A tool for developing software for SoC FPGAs. Arm® Development Studio 5 Intel® SoC FPGA Edition (hereafter DS-5) included in SoC EDS can be used to build and debug application software. This document uses SoC EDS Standard Edition v18.1. SoC EDS Standard Editionv18.1 Notes: Arm® Development Studio 5 Intel® SoC FPGA Edition (paid version) is required for debugging bare-metal applications using the Intel® FPGA Download Cable II (USB-Blaster II). Please refer to the following site for how to install SoC EDS. How to install SoC EDS |
| 4 | Cyclone V SoC Development Kit or Arria V SoC Development Kit |
This is a development kit used as a target board in the explanations in this document. Cyclone V SoCDevelopment Kit Arria V SoC Development Kit |
| 5 | Bare metal sample application | This is the bare metal sample application used in the explanations in this document. This bare metal application is a simple application that just displays a “Hello World!” message over UART. If you want to actually check the operation, please obtain the following files together with this document. Altera-SoCFPGA-HardwareLib-Unhosted-CVGNU.tar.gz This document assumes that Altera-SoCFPGA-HardwareLib-Unhosted-CVGNU.tar.gz is stored in C:\Temp. Notes: You do not need to download the hardware design (.sof file) to the FPGA to run this bare metal sample application. |
| 6 | Terminal emulation software | A serial terminal software is required to use this sample. This article uses freeware software called "Tera Term". Download Tera TermURLs Notes: In Tera Term, set the following for the valid COM port when connecting to the UART of the target board. ・ Baud rate 115200 bps ・ 8-bit data ・ No parity ・ 1 stop bit ・ No flow control |
Notes:
This document assumes basic knowledge of Quartus Prime, SoC EDS, bsp-editor (PreloaderGenerator), and DS-5.
Document
SoCFPGA_Baremetal_QSPI_Boot_CV_AV_v181_r1__1.pdf
Tool version: Document for Ver.18.1 (Rev.1)
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