■ Things to prepare

Quartus® Prime Standard Edition

or Lite Edition (free)

ModelSim* - Intel® FPGA Edition

or

ModelSim - Intel FPGA Starter Edition (Free)

MAX® 10 FPGA Development Kit

Please contact us for consideration and purchase.

(Also available at Macnica Mouser.)

■ Development board connection configuration

The pushbutton [S1] and LED [LED0] are connected on the board as shown.

The LED turns on when the push button is pressed and turns off when the push button is released.

If you just read this explanation, you might think, "What, it's just connecting wires!"

That's right!

Simply connect the FPGA pin that the push button is connected to and the FPGA pin that is connected to the LED.

But connecting...how...?

An FPGA is just an empty box. (*This is an image only.)

So, the FPGA receives the input signal from the push button, passes through the FPGA,

Let's design a ``digital logic circuit'' to output that signal to an LED.

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■ Start designing with Quartus Prime!

Using the Intel FPGA development software Quartus Prime,

Proceed with the work based on the flow introduced on the Intel FPGA development flow/top page.

(For shortcuts to each task, click the items on the left side of the screen to use them.)

1. Design a logic circuit

1-1.

Create a project.

File ➤ New Project Wizard

Here we set the project name and top level entity name to presspb_led.

For the target device, select 10M50DAF484C6GES of the MAX 10 family.

1-2.

Open the working sheet for VHDL or Verilog HDL from the Quartus Prime menu below,

A logic circuit (hereafter referred to as a design) is written in HDL language.

File ➤ New ➤ Design File category ➤ VHDL File or Verilog HDL File

The sample looks like this.

-- VHDL sample : presspb_led.vhd
library ieee; use ieee.std_logic_1164.all;
entity presspb_led is port ( PB : in std_logic; LED : out std_logic ); end;
architecture rtl of presspb_led is begin LED <= PB; end rtl;

// Verilog HDL sample : presspb_led.v
module presspb_led ( input PB, output LED );
assign LED = PB;
endmodule

1-3.

Save the design file using the following menu of Quartus Prime.

Here, the file names are presspb_led.vhd and presspb_led.v.

File ➤ Save As

1-4.

Execute the following menu of Quartus Prime to check for any description errors and build the database.

Processing ➤ Start ➤ Start Analysis & Elaboration

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2. Do logic simulation

With ModelSim - Intel FPGA Edition or ModelSim - Intel FPGA Starter Edition

Perform RTL-level simulation of your own design.

・Please refer to this content for the environment settings and basic work flow for execution.

・Please download the testbench file for this design from the link below.

Save it in your project folder and rename the file to testbench.vhd / testbench.v.

2-1.

Set up NativeLink simulation from the Quartus Prime menu below.

Assignments ➤ Settings ➤ EDA Tool Settings ➤ Simulation

Here, set as follows.

2-2.

Within the NativeLink settings select Compile test bench and click the Test Benches button.

Click the New button in the Test Benches window to set up the New Test Benches Settings dialog Box.

Here, set as follows.

Close each window with OK.

2-3.

Execute function simulation with NativeLink from the following menu of Quartus Prime.

Tools menu ➤ Run Simulation Tool ➤ RTL Simulation

ModelSim - Intel FPGA Edition operations are automatically performed and waveforms are displayed in the Wave window.

Check if this waveform is the expected operation.

2-4.

Select Simulate ➤ End Simulation from the ModelSim - Intel FPGA Edition menu to end the simulation.

Then select File ➤ Quit to close the ModelSim - Intel FPGA Edition GUI.

2-5. (Optional work.)

Set the following menus in Quartus Prime back to None.

Assignments ➤ Settings ➤ EDA Tool Settings ➤ Simulation

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3. Set constraints

Work returns to Quartus Prime.

3-1.

Specifies the pin number.

Assign the input pin (PB) and output pin (LED) on your design to the desired MAX 10 pin numbers and set the I/O standard.

In the Pin Planner, set the Location (pin number) and I/O Standard like this:

The reason why the I/O Standard of each pin is set to "1.5 V"

Pins T20, L22 of MAX 10 on MAX 10 FPGA Development Kit belong to I/O Bank 5.

This is because the power supply for that I/O bank ^(*) is supplied with 1.5 V.

That's why the LED pull-up power supply is also 1.5 V.

[Reference information] What is an I/O bank?

3-2.
Select a configuration mode.

How to use MAX 10's CFM (flash memory for configuration) = what mode to choose

This time, select "Single Compressed Image".

Assignments ➤ Device ➤ Device and Options ➤ Configuration ➤ Configuration mode

3-3.

​Create & set timing constraints for your design.

This time it has nothing to do with clock control and is not a logic circuit that requires speed.

Since it is a super simple operation of Pin to Pin, it is omitted.

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4. Compile

Now it's time to compile the design.

 

Processing ➤ Start Compilation

Logic synthesis and placement and routing are executed, and program data to be written inside the FPGA is generated at the same time.

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5. Verify timing

After compiling, examine the generated compilation report.

In addition, I will omit it in this L blinking

In normal development, you check the contents of the Timing Analyzer report and verify that the timing meets the conditions given by the timing constraints.

If there is a timing violation, we will try to improve it while performing detailed analysis using Timing Analyzer.

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6. Do programming

Start Programmer from the following menu of Quartus Prime and transfer data to MAX 10 on the board.

Tools ➤ Programmer

Compiling MAX 10 generates two types of writing files (.sof / .pof).

This time I want to transfer data for the purpose of checking the operation on the actual machine (that is, debugging)

Download the SOF file to CRAM (Configuration RAM) inside MAX 10.

Connect the MAX 10 FPGA development kit to your computer with a mini-USB cable.

Connect the power cable and apply power to the board (On).

[Reference information] Installing the USB-Blaster II driver

In Programmer, select USB-Blaster II from Hardware Setup.

After setting presspb_led.sof, click the Start button♪

Data transfer is complete when the Progress bar in the Programmer reaches 100%.

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■ Let's go! Operation verification on actual machine

Click the push button [S1] on the MAX 10 FPGA development kit.

(Click the image to see the video.)

Oh, L blinking! I made it!

Since we just wrote to the CRAM inside the MAX 10, the data will be erased when the board is powered off.

To write the programming data to the CFM (Non-Volatile Flash Memory Area) inside the MAX 10 after debugging is finished.

Download presspb_led.pof with Programmer.

Now even if you power off the board, the data will not be lost.

Because MAX 10 is FPGA = programmable device

If you change the output pin number to the pin number connected to another LED while keeping the logic circuit this time as it is

The position of the lit LED also changes. Please try it!

 

This time it was a simple circuit that just connects pins to make it easy to understand.

If you expand more and more and make a logic circuit, various possibilities will spread.

Everyone please try it.

For the first LED flashing with Intel FPGA [Part 2], I would like to put Nios® II into the FPGA and flash it.

looking forward to!

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■ Sample project

The design of L Chika this time can be created from scratch as per this content

If you want to use the actual machine immediately, please use the sample project below.

* Please refer to ``Restoring Archived Projects'' in Quartus Prime - Managing Projects for how to extract QAR files.

* For information on how to restore a project, please refer to ``How to start an existing project'' in "Quartus Prime Beginner's Guide - How to Create a Project".

This series of work in Quartus Prime can also be seen in this video.

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