2. Do logic simulation

I will write a test bench to verify the operation of the logic circuits I have written myself.
Next, run a simulation using ModelSim* - Altera® FPGA Edition (Starter Edition is also acceptable).

Reference technical content
Let's start! Test bench

3. Set constraints

Quartus® Prime again.

3-1. Set pin layout and I/Ostandard

​Specify pin numbers on the device for the input and output pins on the logic circuit. At the same time, it also sets the I/O standard for those pins.

Cyclone® V GX devices have separate power supplies for the transceiver block and the FPGA.

The power supply on the FPGA side is divided into eight blocks, which Altera® FPGAs refer to as I/O banks.

Each I/O pin belongs to one of the I/O banks and is powered for that I/O bank.

The power supplies for each I/O bank can supply different voltages, allowing a single device to support different I/O standards and interface with different ICs.
The user may ask, “What I/O standard should be concentrated in which I/O bank?” or “This I/O bank will be powered by △ volts, so we can lay out this I/O pin.” layout can be freely configured.

How many/how the banks are divided depends on the device family, so be sure to check the device handbook, pinout file, etc.
Since this Beryll board is an evaluation board, the power supply configuration and pin layout have been decided.

Let's set the pin numbers and I/O standards according to the Beryll board specifications as shown in the table below.

In addition, FPGA user I/O pins have selectable output current values, which can also be set in the Quartus® Prime Pin Planner (option name: Current Strength). The output current affects the FPGA's power consumption and noise during signal output, so it's nice to be able to control it.
The current value that can be set differs depending on the target device and the I/O standard to be set, so be sure to check the handbook for the device you are using.
In this demonstration, there is only one output pin that drives the LED, and if you look closely at the board diagram, the H19 pin is designed to light up the LED when it outputs GND. Since there is no drive purpose when outputting High, the current is set to 4mA, which is the smallest, but there is no problem with the default.

3-2. Reserve unused user I/O pins for specific attributes

Typically for user-built boards, Quartus® Prime also programs each unused user I/O pin with appropriate attributes for that pin, depending on how it is handled on the board. set as follows.

For example, if an unused user I/O pin is not connected to anything on the board (unconnected), Quartus® Prime will specify an “input with internal weak pull-up” or “output” for that pin. ” will be booked as

For details on setting methods and setting items, refer to "Quartus® Prime Getting Started Guide - How to Set Device Options" and "Quartus® Prime Getting Started Guide - How to Assign Pins".
In the case of Beryll, all user I/O pins except for the 8 user I/O pins (AC10/T11/W11/Y11/AE10/AE13/Y15/G7) are somehow connected, so they are reserved for tri-state inputs. To do.

The 8 unused and unconnected user I/O pins (AC10/T11/W11/Y11/AE10/AE13/Y15/G7) are now reserved for GND output and I/O standards according to Beryll's power specifications set.
Also, Flash ROM/SRAM/DDR3 SDRAM is not used in this demo, so to disable the chip select (CS) pin of each memory device, reserve the pin on the Cyclone® VGX side for VCC output and set the I /O Sets the standard and output current value.

3-3.Set device pin options

The INIT_DONE pin (Pin U19) is boarded for use as an option pin, so enable the option.
From the Assignments menu > Device > Device and Pin Options > General category
Enable INIT_DONE output = On

3-4.Select configuration mode

Beryll has an EPCS128SI16N as the Cyclone® V GX configuration ROM, and the Cyclone® V GX MSEL pins are connected to MSEL[4:0]=10011.

In other words, the data transfer method is the specification of the active serial configuration mode (AS mode).
This time,

• Configuration scheme: Active Serial x1 (can use Configuration Device)
• Configuration mode: Standard
• Use configuration device = On / EPCS128
• Leave everything else as default.

3-5. For logic circuitsCreate and Register Timing Constraints

This time it is the clock control circuit. Create an SDC file for timing constraints.

The first and second lines are clock definitions.
The third line is the constraint command for the clock multiplexer configuration.
The circuit configuration of this demo (Pattern B) is a configuration that selects two clocks with different frequencies. It is necessary to perform timing analysis to see if it works with both 50MHz and 125MHz clocks. However, after the clock is selected, the 50MHz and 125MHz clocks will not be valid at the same time, so constrain them with the -exclusive option of the set_clock_groups command.
The fifth line is a command to automatically calculate clock variations and reflect them in timing analysis.
Lines 7 to 9 are commands for excluding from timing analysis targets.
The reset signal (ACLR) and clock switching signal (BUTTON) are controlled by pushing a push button. Considering the fact that it is an asynchronous input and the speed at which a person presses, there is no need for timing analysis, so I excluded it.

After creating the timing constraints, register the SDC file in the Quartus® Prime Assignments menu > Settings > TimeQuest Timing Analyzer.

4. Compile

To execute compilation, click the Start Compilation button♪

Logic synthesis and place-and-route are now executed, and the program data to be executed inside the FPGA is also generated at the same time.

5. Verify timing

In the compilation report generated after compilation, check the TimeQuest Timing Analyzer report section and verify that the result satisfies the conditions given by the timing constraints.

In the case of Cyclone® V GX, there are four timing models used for timing analysis (worst-case/maximum operating temperature, worst-case/minimum operating temperature, fastest-case/maximum operating temperature, and fastest-case/minimum operating temperature), and the timing must meet the desired values in all models.
The results calculated for each model and compared to the requirements of the created SDC are saved in their respective folders. If any item does not meet the requirements, the item name will be displayed in red, but since everything is in black text, you can see at a glance that the requirements have been met.
If there are timing violations, please use Timing Aligner to analyze and improve the situation.

Finally, let's write the design we've created onto the Beryll board and run it.
Blinking an LED with clock synchronization using Beryll FPGA! [#3/3] (continued)

Beryll's FPGA flashes by clock synchronization! series

Beryll's FPGA flashes by clock synchronization! [#1/3]
Beryll's FPGA flashes by clock synchronization! [#2/3]
Beryll's FPGA flashes by clock synchronization! [#3/3]

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